Career records & work history
Lawyers & Attorneys
Victor Ma - Lawyer
Office:
Freshfields Bruckhaus Deringer LLP
ISLN:
1000922350
Admitted:
2020
Victor M Ma, 56611 Laurel Glen Ter, Fremont, CA 94539
Victor Ma Phones & Addresses
611 Laurel Glen Ter, Fremont, CA 94539
Hudson, MA
5642 Strawflower Ln, San Jose, CA 95118 408-2669605
Champaign, IL
Brooklyn, NY
Campbell, CA
Alameda, CA
5347 Nordica Ave, Fremont, CA 94536
Work
Company:
Agility - Burlingame, CA May 2012
Position:
Business development executive
Education
School / High School:
University of California, Berkeley- Berkeley, CA May 2007
Specialities:
Bachelor of Arts in Political Economy of Industrial Societies
Mentions for Victor M Ma
Resumes & CV records
Resumes
Physical Design Architect
Location:
San Francisco, CA
Industry:
Computer Hardware
Work:
Apple
Physical Design Architect Amd 2010 - Mar 2012
Senior Project Manager Amd 2005 - 2009
Senior Physical Design Manager Amd 2003 - 2005
Staff Cad Engineer Procket Networks 2000 - 2003
Mts Sequence Design 1997 - 1999
Application Engineer Avanti 1997 - 1998
Various Digital Equipment Corp 1992 - 1996
Cad Engineer
Physical Design Architect Amd 2010 - Mar 2012
Senior Project Manager Amd 2005 - 2009
Senior Physical Design Manager Amd 2003 - 2005
Staff Cad Engineer Procket Networks 2000 - 2003
Mts Sequence Design 1997 - 1999
Application Engineer Avanti 1997 - 1998
Various Digital Equipment Corp 1992 - 1996
Cad Engineer
Education:
University of Illinois at Urbana - Champaign 1990 - 1992
Master of Science, Masters, Electrical Engineering Columbia Engineering 1986 - 1990
Bachelors, Bachelor of Science, Electrical Engineering
Master of Science, Masters, Electrical Engineering Columbia Engineering 1986 - 1990
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Asic, Physical Design, Eda, Tcl, Formal Verification, Floorplanning, Perl
Victor Ma
U S Postal Letter Carrier
Work:
United States Postal Service
U S Postal Letter Carrier
U S Postal Letter Carrier
Victor Ma
Victor Ma
Master's Candidate At San Francisco State University
Location:
San Francisco Bay Area
Industry:
Higher Education
Victor Ma - Fremont, CA
Work:
Agility - Burlingame, CA May 2012 to Aug 2013
Business Development Executive Air Tiger Express - South San Francisco, CA Mar 2011 to Apr 2012
Sales Executive East West Bank - San Francisco, CA Aug 2008 to Apr 2010
Portfolio Analyst East West Bank - San Francisco, CA May 2008 to Aug 2008
Operations Assistant
Business Development Executive Air Tiger Express - South San Francisco, CA Mar 2011 to Apr 2012
Sales Executive East West Bank - San Francisco, CA Aug 2008 to Apr 2010
Portfolio Analyst East West Bank - San Francisco, CA May 2008 to Aug 2008
Operations Assistant
Education:
University of California, Berkeley - Berkeley, CA May 2007
Bachelor of Arts in Political Economy of Industrial Societies
Bachelor of Arts in Political Economy of Industrial Societies
Publications & IP owners
Us Patents
Integrated Circuit Chip With Repeater Flops And Method For Automated Design Of Same
US Patent:
2008006, Mar 13, 2008
Filed:
Aug 17, 2007
Appl. No.:
11/840660
Inventors:
Stuart Taylor - San Jose CA, US
Victor Ma - Fremont CA, US
Bharat Patel - San Jose CA, US
Victor Ma - Fremont CA, US
Bharat Patel - San Jose CA, US
International Classification:
G06F 17/50
H03K 19/0175
H03K 19/0175
US Classification:
716010000, 326062000
Abstract:
An integrated circuit (IC) chip having repeaters for propagating signals along relatively long wires that extend between and among lower-level physical blocks of the IC chip, wherein the repeaters are implemented as clocked flip-flops (or “repeater flops”). A method for automatically inserting and allocating such repeater flops during the logical and physical design of the IC chip is also provided.
Integrated Circuit Chip With Repeater Flops And Methods For Automated Design Of Same
US Patent:
2012022, Aug 30, 2012
Filed:
Apr 30, 2012
Appl. No.:
13/460747
Inventors:
Stuart A. Taylor - San Jose CA, US
Victor Ma - Fremont CA, US
Bharat Patel - San Jose CA, US
Victor Ma - Fremont CA, US
Bharat Patel - San Jose CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 17/50
US Classification:
716114
Abstract:
An integrated circuit (IC) chip having repeaters for propagating signals along relatively long wires that extend between and among lower-level physical blocks of the IC chip, wherein the repeaters are implemented as clocked flip-flops (or “repeater flops”). A method for automatically inserting and allocating such repeater flops during the logical and physical design of the IC chip is also provided.
Compact Metal Connect And/Or Disconnect Structures
US Patent:
2012031, Dec 13, 2012
Filed:
Jun 9, 2011
Appl. No.:
13/156399
Inventors:
Omid Rowhani - Newmarket, CA
Victor M. Ma - Fremont CA, US
Victor M. Ma - Fremont CA, US
International Classification:
H01L 23/522
G06F 17/50
H01L 21/768
G06F 17/50
H01L 21/768
US Classification:
257774, 438618, 716 50, 257E23145, 257E21575
Abstract:
Embodiments of present invention provide methods and apparatuses for connecting and/or disconnecting nodes in a semiconductor device. Embodiments of the apparatus may include a plurality of metal layers formed above a substrate and an interconnect structure formed between first and second nodes in the plurality of metal layers. The interconnect structure includes one or more metal lines formed in each of the metal layers. The metal lines are connected by a plurality of vias. Modifying one of the metal lines in any one of the metal layers changes an electrical connection between the first and second nodes.
Possible Relatives
NOTICE: You may not use BackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. BackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.